74HC595D is a high-speed silicon gate CMOS device with pins compatible with low-power Schottky TTL circuits (LSTTL). It complies with JEDEC standard No.7A. Itconsists of eight serial shift registers with storage registers and three state outputs. The shift register and storage register have separate clocks. Data in shift clock SH_ When the rising edge of CP arrives, shift transmission is performed, while the storage clock ST_ When the rising edge of CP arrives, it is transferred from the shift register to the storage register. If two clocks are connected together, the data on the shift register is always one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a cascaded serial output (Q7 '), as well as an asynchronous reset (effective at low levels).
The storage register has an eight bit parallel bus driver output with a three state output. When the output enable end (OE) is at low level, the output end is normal output. Conversely, when OE is at high level, the output is in high resistance off state.
The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). — When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register — asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input ( — — CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15V. This enables the device to be used in HIGH-to-LOW level shifting applications.
The 74HC4094D is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
