74HC595D is a high-speed silicon gate CMOS device with pins compatible with low-power Schottky TTL circuits (LSTTL). It complies with JEDEC standard No.7A. Itconsists of eight serial shift registers with storage registers and three state outputs. The shift register and storage register have separate clocks. Data in shift clock SH_ When the rising edge of CP arrives, shift transmission is performed, while the storage clock ST_  When the rising edge of CP arrives, it is transferred from the shift register to the storage register. If two clocks are connected together, the data on the shift  register is always one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a cascaded serial output (Q7 '), as well as an asynchronous reset (effective at low levels).

The storage register has an eight bit parallel bus driver output with a three  state output. When the output enable end (OE) is at low level, the output end is  normal output. Conversely, when OE is at high level, the output is in high resistance off state.